Edge AI hardware/algorithm co-design Researchers from the University of Massachusetts Amherst and TetraMem combined memristive analog in-memory computing hardware with hyperdimensional computing algorithms to improve AI edge device efficiency.…
Hyperdimensional computing represents information using large mathemat…
The platform can both encode language features and process language id…
“The encoding part leverages the intrinsic randomness of memristive de…
Semiconductor Earnings Roundup: Revenue, Growth and Takeaways
Earnings were strong across all chip industry sectors this quarter, with 11 companies posting triple-digit growth, and all but 2 of the 80 companies reported here were in positive territory.…
The hottest growth areas were AI infrastructure, memory, advanced pack…
Companies tied to HBM, data centers and AI accelerators generally post…
Quarterly revenue increase/decrease percentages are in comparison to t…
New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.…
5D PIM Chiplet Architectures Washington State University, University o…
imec From Lithography to Nanoimprint: Physics-Based, Data-Driven, and …
5D Systems A*STAR Self-Focusing Control for Depth-Precise Wafer Slicin…
Controlling Voltage Droop In 2.5D PIM Chiplet Architectures (Washington St., UW-Madison)
Researchers from Washington State University and University of Wisconsin–Madison published a technical paper titled “ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.…
5D PIM Chiplet Architectures.
” Abstract “Processing-in-memory (PIM)-based 2.
5D multi-chiplet platforms are enablers for machine learning (ML) work…
Key Takeaways: AI data centers use exponentially increasing amounts of power; the challenge now is converting high-voltage AC grid power to low-voltage chips that require DC.…
The 800VDC architecture for AI data centers is more efficient than 48V…
It also uses less copper.
Solid-state transformers support the two-stage conversion architecture…
Packet-Based NPUs In The LLM Era: From Compute-Bound CNNs To Memory-Bound Edge And Automotive Workloads
Many Semiconductor Engineering readers know the basic story behind Expedera’s Origin NPU IP architecture: packets instead of layers, higher MAC utilization, and less gratuitous movement of activations to external memory.…
What’s changing now is the workload mix.
Vision-only edge processors are giving way to systems where LLMs, VLMs…
In terms of NPU design, what are the implications when the dominant ed…
What Self-Verifying Means In Agentic EDA Workflows And Why It Matters
Last month, we covered the architectural decisions behind a production-ready EDA AI agent: domain grounding, scalable orchestration across a fragmented tool ecosystem, native interpretation of EDA data formats, and security at the execution layer.…
These are the foundations upon which successful agentic workflows for …
When an agent is executing a long-running EDA workflow autonomously, m…
Why deterministic physics-based EDA engines matter The answer is physi…
Key Takeaways: Hardware and software development have traditionally been disconnected, creating little opportunity to optimize system-level performance and energy consumption.…
Development swings between specialized and generalized solutions based…
Energy and thermal concerns are forcing more companies to create speci…
Thirty years ago, there was a lot of interest in hardware/software co-…
Key Takeaways: The push toward 1-megawatt racks is forcing fundamental changes in data center architecture, including cooling, power delivery, rack design, and 3D-IC packaging.…
Higher rack densities may not be the only viable scaling path, as opti…
AI and agentic workloads are shifting systems from average-power assum…
Data centers are gearing up for a future in which a single rack could …