Managing Thermal Expansion And Electromigration Through Interposer Design

Key Takeaways:

• To increase interconnect density to support the bandwidth requirements of AI workloads, manufacturers are turning to 2.5D and 3D packaging architectures.
• While 2.5D interposers, as passive components, avoid some of the reliability challenges of 3D packages, they are still vulnerable to thermomechanical failure, with many different layers having different coefficients of thermal expansion.
• Increasing interconnect density also makes it important to manage electromigration risks. The microstructure of copper redistribution layers can make electromigration more or less likely.

As scaling transistors laterally becomes more difficult, manufacturers are turning to vertical transistor designs such as CFETs and vertical packaging to increase device density. At the same time, the enormous bandwidth needed for AI workloads is driving increases in interconnect density between chips.

Yet the fundamental aims of device packaging have not changed — protecting the chip from damage, and connecting micron-scale bond pads on the chip to other chips and to millimeter-scale features on the circuit board.

Currently, hybrid bonding achieves the highest available interconnect density between chips. So-called 3D packages use hybrid bonding to stack chips vertically, achieving the maximum circuit density in the minimum footprint. Through-silicon vias (TSVs) transport signals to the bottom of each chip as needed to connect to either the next chip in the stack or the underlying package substrate.

3D packages require close integration between the component chips, down to alignment between copper protrusions on one and bond pads on the other. They also pose substantial testing and reliability concerns. Heat dissipation is especially difficult because the surface area of the stacked chip increases more slowly than the volume of active devices. Heat can cause TSVs to expand during operation, creating stress and potentially causing cracks and delamination. Because all layers in the stack include active devices, heat flow and signal paths can affect each other in ways that are difficult to predict.

In contrast, 2.5D packages offer a more flexible option. In these packages, chips are placed on an interposer that redistributes signals from the bond pads on each chip to other chips or to the package substrate. The interposer is a passive component, with wiring and possibly capacitors and resistors, but no transistors or other switches. It is both simpler to model and simpler to manufacture than active circuits, avoiding some of the reliability issues of 3D packages.

In theory, the component chips in a 2.5D package are independent of each other. If the pad layout on one of the component chips changes, the interposer design will need to change, but not the designs of the other chips. Conceptually, an interposer functions like a circuit board with very dense wiring.

Complex structures, complex thermal behavior
However, a 2.5D package still must dissipate heat, provide mechanical support, and so on. A change to one chip might change both the heat flow and the thermomechanical behavior of the package. In fact, Hakjun Kim and colleagues at Seoul National University found that thermomechanical failure is the most challenging reliability issue for 2.5D packages.[^⁠1] Because materials have different coefficients of thermal expansion (CTE), temperature changes during manufacturing and resistive heating during operation will cause them to expand and contract at different rates.

In a 2.5D package, the chip(s) are typically silicon with copper interconnects, which have a low CTE. The package substrate, molding compound, and underfill are typically organic materials with high CTEs. 2.5D packages span a bewildering variety of options, with interposers that potentially include photonics components, microfluidic cooling, and more. Silicon and polyimide are two of the most common alternatives, both with embedded copper lines.

In a simple package with only one chip, it’s relatively straightforward to model expansion and contraction during manufacturing. Reflow ovens and other processes heat and cool the entire package at once. In operation, though, heat flow depends on signal paths and workflows within the chip. Temperature gradients within the chip combined with CTE differences between layers lead to complex stress patterns.

In a package with more than one chip, both manufacturing stress and operational stress are more difficult to model. For instance, two adjacent chips might create opposing stresses on the underlying interposer and substrate. Rather than a simple concave or convex bow, the stress field could be a saddle or other complex shape. Kim explained that stiffening the package in one area can increase stress in other areas. For example, if the chips and interposer expand more than the substrate, the resulting tensile stress can warp the substrate. Substantial warpage can cause elongated or failed solder bonds. Yet stiffening the substrate to prevent warpage does not remove the stress, but transfers it elsewhere in the package. The bond between the interposer and the substrate might fail, or the redistribution layers might delaminate.

Ming-Sheng Luo and colleagues at South China University of Technology developed a finite element model of a simple 2.5D package with two adjacent chips and three layers of redistribution interconnects. They identified the space between chips and the connection between the interposer and the molding compound as particularly failure-prone regions. For larger packages, they suggested adding dummy chips — bare silicon coupons — to help balance stresses within the package.[^⁠2]

Luo also observed that, depending on the system’s environment, moisture absorption by the package materials might be relevant, as well. Different materials will absorb moisture and expand due to differing absorption rates. Moreover, a material’s hygroscopic behavior will not necessarily parallel its thermal behavior.

Managing electromigration
Electromigration, the next major cause of packaging failures, has not historically been a major concern for logic and memory devices. It is an effect of current density, though, so electromigration risks increase as the current density in the package rises. Yi-Quan Lin and colleagues at National Yang Ming Chiao Tung University (Hsinchu, Taiwan) varied the copper electroplating chemistry to produce lines with either nanocrystalline or nanotwinned grain structure.

Varying the crystal structure to control electromigration has less impact on circuit resistance than dopants of alloying elements, and adds less process complexity than trench liners and similar solutions. In Lin’s study, nanocrystalline copper actually reduced electromigration resistance, apparently because grain boundaries facilitated diffusion. Nanotwinned copper, particularly after annealing, had a strong (111) texture and a large fraction of coherent twin boundaries. This structure suppressed oxide formation and void generation along grain boundaries.[^⁠3] Similar studies at ASE Group examined electromigration behavior in situ in de-capsulated RDL structures. Smaller grains achieved lifetimes approximately seven times longer than lines with larger grains.[^⁠4]

Modeling for the future

Fig 1: Schematic illustration of 2.5D package with three chiplets and an eight-layer silicon interposer.[5]

The complexity of 2.5D packages, combined with the difference in scale between the individual bond pads and the overall package makes predictive modeling challenging. Finite element analysis of individual regions is straightforward, but the number of regions that must be considered is computationally prohibitive. Researchers are beginning to develop deep learning surrogate models that can reduce the need for finite element analysis. Early results suggest this approach may offer a practical pathway to scalable modeling of warpage and other non-linear behaviors.[⁠5]

References

1. H. Kim, et al., “Thermomechanical Challenges of 2.5-D Packaging: A Review of Warpage and Interconnect Reliability,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 10, pp. 1624-1641, Oct. 2023, doi: 10.1109/TCPMT.2023.3317383.
2. M. -S. Luo, et al., “A Comprehensive Simulation Study on Cu Trace Damage and Cu/Polyimide Interface Delamination of RDLs in Fan-Out Wafer Level Package Under Hygro-Thermo-Mechanical Loads,” 2024 IEEE 26th Electronics Packaging Technology Conference (EPTC), Singapore, 2024, pp. 841-847, doi: 10.1109/EPTC62800.2024.10909933.
3. Yi-Quan Lin, et al., “Impact of microstructure engineering on electromigration resistance of copper redistribution lines,” Journal of Materials Research and Technology, Volume 39, 2025, Pages 3076-3086, ISSN 2238-7854, https://doi.org/10.1016/j.jmrt.2025.10.037.
4. M. -Y. Tsai, et al., “Effect of Microstructure on the Electromigration Performance of 2- μm-Cu Redistribution Line under In-situ SEM Observation,” 2024 IEEE CPMT Symposium Japan (ICSJ), Kyoto, Japan, 2024, pp. 184-187, doi: 10.1109/ICSJ62869.2024.10804753.
5. Yang, C., et al., “Deep Learning-Enabled Multiscale Strategy for Rapid and Accurate Warpage Prediction of Interposer Routing Interconnects.” Int. J. of Precis. Eng. and Manuf.-Green Tech. (2026). https://doi.org/10.1007/s40684-026-00914-5

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