Streamlining 3D-IC Design: Substrate, Finalization, And Tapeout

By Keith Felton and Todd Burkholder

The superior performance, functionality, and smaller form factors of 3D-ICs are propelling advances in the semiconductor industry. Unlike traditional 2D-ICs, 3D-ICs vertically stack multiple active device layers connected with through-silicon vias. This vertical integration delivers many benefits but introduces further complexity in design and manufacturing, particularly in substrate implementation, design finalization, and fabrication tapeout.

In the first two articles in this series (published in this journal in June and July), we covered the first four steps toward streamlining the 3D-IC design process. With these steps completed, the design team is ready to perform substrate implementation strategies, finalize the substrate design, and tapeout the fabrication mask set. We will examine these steps in this article.

Substrate implementation strategies

The substrate forms the foundation of any 3D-IC design, acting as the integration platform for chiplets, memory, and interposers. Effective substrate implementation is crucial for signal integrity, power delivery, and overall system reliability.

The implementation process starts by importing a carefully floorplanned design scenario and a thoroughly validated system netlist. This netlist should have undergone predictive multiphysics analysis to prevent potential issues. In a streamlined 3D-IC workflow, the optimized design scenario is developed using the specialized Siemens Innovator3D IC Integrator software and is forward-annotated into the Innovator3D IC Layout substrate implementation tool, thus ensuring continuity and accuracy all the way from planning to layout.

Fig. 1: Signal path “sketch plan” proposals as defined in Innovator3D IC Integrator.

The next step is to load the specific substrate technology rules, provided by the substrate supplier or foundry/OSAT. In traditional IC design, these rules are delivered as process design kits (PDKs) along with the design rule manual. For 3D-IC package design, PDKs are still evolving, but many foundries and Tier 1 OSATs offer digital design data as assembly design kits or package assembly design kits. The emerging IEEE 3Dblox file also defines a modular syntax for describing components and their connectivity. Regardless of the format, this data must be accurately loaded into the physical implementation tool for correct-by-construction design.

With all design data and technology rules loaded, the next step is finalizing the substrate/interposer power delivery network (PDN). If the initial design scenario was comprehensively floorplanned using a pathfinding and prototyping tool, the imported scenario likely contains prototyped PDNs. These preliminary PDNs require meticulous finalization to comply with the fabricator’s detailed design rules, including verifying space for micro-bump and bump breakout patterns, and sufficient signal routing channels. It’s often necessary to replace simpler prototype via structures with more complex, fabrication-ready ones.

Fig. 2: Chiplet-to-chiplet interface pin field breakout routing using Innovator3D IC Layout’s embedded interface routing automation.

Heterogeneously integrated designs often incorporate multiple channels, allowing for circuit and route pattern replication. This technique shortens design cycles and enhances efficiency, as changes to a master (“seed”) pattern automatically propagate to all replicated instances. High-bandwidth memory arrays are prime candidates for such replication. While a simple copy-paste method can be used, it requires manual updates for each pasted instance if changes are needed.

A more efficient approach uses substrate design tools supporting intelligent circuit replication, often via physical reuse blocks. With this capability, a seed instance is identified and replicated, maintaining a vital link to the original. If connectivity or assignment changes are necessary, updating the seed propagates these changes to all or selected instances, significantly reducing design time and potential errors.

Detailed interconnect routing

Route plans, established by the Innovator3D IC Integrator pathfinding and prototyping cockpit, suggest signal and interface paths for connectivity. These preliminary plans, however, require meticulous tuning to accommodate the detailed substrate design spacing rules provided by the fabricator.

The initial phase of this detailed interconnect routing focuses on completing critical interfaces, typically between logic devices and memory and between logic devices themselves. The most challenging aspect often involves successfully routing signals into and out of the micro-bump pin fields of chiplets and HBM devices to external connections. Routing real estate frequently necessitates complex shielded via arrays for differential signals. The efficiency of this process is significantly enhanced because Innovator3D IC Integrator can automatically create complex via arrays and store them as library elements for reuse.

After critical replicated circuitry and interface routing are finalized, the remaining connectivity routing can be completed through manual, automatic, or semi-automatic methods. Many designers prefer a semi-automatic approach, balancing automation and user control. Tools with “sketch router” capabilities, for instance, offer multiple modes and options to precisely control route flow, from one-button automation to user-defined path specifications. Innovator3D IC Integrator features like push, shove, and hug modes intelligently manipulate route segments around and over objects, such as vias or device pads, optimizing routing efficiency and adherence to design rules.

Fig. 3: Semi-automated routing using the sketch router.

Finalizing the substrate design for fabrication

Before design can proceed to tapeout, it is necessary to finalize the substrate design, ensuring it meets fabrication requirements and addressing potential manufacturing challenges. These steps include optimizing the PDN, adding essential fiducial markers, and preparing the design for thermal and mask design rule check (DRC) signoff.

Following PDN structure finalization, the focus shifts to optimizing the PDN for fabrication yield and reliability. PDNs are typically large metal-filled areas (“metal pours”). Such extensive metal areas can cause fabrication issues like outgassing, where gas bubbles form during manufacturing and can lead to layer delamination and substrate warping. This can be mitigated by inserting degassing voids within these metal areas. Substrate fabricators provide rules for these voids, which vary in size and shape and are inserted in areas exceeding a certain dimension. This process, if manual, can be tedious; however, dedicated substrate design tools, like Innovator3D IC Layout, offer utilities for multi-pass degassing void insertion, allowing selection of void shapes and sizes that meet fabricator requirements and can intelligently avoid inserting voids under differential signals to prevent timing issues.

Fig. 4: Innovator3D IC Layout degassing void insertion utility.

After degassing is complete, the next step is metal balancing. After PDN planes are finalized and degassed, the metal ratio across design layers can become non-uniform, leading to substrate warpage during fabrication or package assembly. To counteract this, tools calculate metal density by redistribution layers (RDL) and by defined area for each RDL layer. If an RDL layer is within the fabricator’s overall metal density range, attention then shifts to individual areas. If an area has excessive metal, additional degassing voids can be inserted. Conversely, if there is insufficient metal, necessary dummy metal fill for deficient areas can be created, ensuring compliance with fabricator requirements. These metal blocks are then re-imported into the design.

Fiducial markers enable operators and automated systems to quickly determine a particular location within the die, which is essential for high-magnification microscopy, micro-probing, or failure analysis. Fiducial markers are distinct, identifiable structures embedded within a die or interposer/substrate. They serve as crucial reference points for locating, aligning, and navigating during various stages of testing, inspection, and de-processing. These markers are essential for accurate fabrication and assembly of multi-chiplet 2.5/3D-IC package designs.

Fig. 5: Dedicated fiducial marker object within Innovator3D IC Layout.

Adding top and bottom die fiducials allows internal-layer, buried dies to be aligned during the manufacturing and assembly process. Additionally, top and bottom metal layer fiducials can be used during the alignment of stacked dies. Historically, fiducial markers were often created manually, a time-consuming and error-prone process. Innovator3D IC Layout, however, features dedicated, intelligent design object classes for fiducial markers, allowing them to be stored, reused, and shared efficiently across designs.

It is imperative to conduct early predictive thermal analysis during the pathfinding and prototyping stages. Issues detected at this time are typically easier and less costly to address. Neglecting predictive analysis can lead to major challenges during the detailed design stage, significantly increasing mitigation efforts. Even with early thermal analysis, there is still a need for final detailed sign-off thermal analysis. To streamline this process, robust integration between the package physical design tool and the thermal analysis solution is crucial for efficient data exchange and accurate simulation.

Fig. 6: Calibre 3DThermal is directly integrated with Innovator3D IC Layout.

Exporting to mask DRC signoff

Before the substrate/interposer mask set can be taped out for fabrication, it must achieve DRC signoff using the fabricator’s PDK. This signoff DRC is typically performed not within the layout tool itself, but in a separate graphical Boolean-based verification tool, using the actual mask set data that will be sent to the fabricator. The fabricator’s PDK is almost universally provided in a format compatible with industry-standard DRC tools, such as Calibre, which address all sign-off requirements. Because Calibre is the industry standard, the consumed mask set can be exported from all substrate/integrator design tools.

Fig. 7: Calibre DRC viewer/explorer.

With the mask set loaded into the DRC tool along with the design rules, results are quickly available, allowing designers to address any identified issues. The advantage of using Innovator3D IC Layout with Calibre is that the Calibre DRC results-viewer is directly integrated. This enables any DRC issues detected by Calibre to be highlighted directly in the Innovator3D IC Layout editor, making debugging a much easier process.

Fig. 8: Calibre DRC results viewer is directly integrated with Innovator3D IC Layout.

After all DRC issues have been thoroughly addressed or formally waived, the designer can create the production mask set, typically in GDSII or the more compact OASIS format. It is often required, and always highly recommended, to re-validate the design using the DRC tool to ensure it is “clean” and that no new issues were inadvertently introduced during mask issue resolution. A clean DRC report signals that the mask set is ready to be sent to the fabricator.

This marks the completion of the detailed design implementation phase, and we are on to our next article in this series, in which we will see why embracing robust data management practices, including diligent management of the design and its design IP sources, meticulous revision control, centralized information hubs, and comprehensive status tracking for traceability, lays a solid foundation for success.

To dive deeper into on how to improve your 3D-IC flow, please check out the new series of eBooks from Siemens on Streamlining 3D-IC design:

1. Creating the 3D Digital Twin
2. Pathfinding the optimal floorplans
3. Finalizing the design scenario
4. Signoff and export
5. Implementation and interface
6. Finalizing substrate design for fabrication
7. Chiplet-to-chiplet signal integrity pathfinding for UCIe
8. Managing the design and its design IP

Todd Burkholder is a senior editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Burkholder began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

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