How Cache Coherency Simplifies AI Software

There was a time when adding hardware simply to make software more efficient was considered wasteful. Every additional hardware feature consumed valuable area, increased power, and added to the design and verification effort. With transistor budgets tightly constrained, hardware was reserved for capabilities that delivered clear performance or functional benefits, while software teams were expected to absorb much of the system’s complexity.

This tradeoff is changing. As software has become a larger portion of product development, designing systems-on-chip (SoCs) to reduce software complexity has become a deliberate architectural choice.

In an AI system, an accelerator may write data to memory and a CPU may then read it, or control information may be shared between them. As CPUs and accelerators exchange more shared data, software tracks whether each processing element is working from the current version or from data that has changed.

Managing shared-data coordination in software adds complexity and can create difficult-to-debug errors, which is why cache coherency is becoming widely adopted in chip hardware. Engineers are turning to cache coherency, a chip-level technology that keeps shared information current, whether it is in memory or cache, so the CPU sees the correct version. By moving more of that management into the coherent interconnect and memory system, the architecture helps make software simpler, more reliable, and faster to develop.

Accelerators share memory

Early accelerator systems often avoided this data management issue by keeping compute resources separated. A CPU might communicate with an accelerator over PCIe, copy data into accelerator memory, send a message, and wait for results. That approach worked when the processor and accelerator operated more independently, but it becomes harder to scale as more shared data moves through the system.

The challenge becomes even more evident in edge AI, where a general-purpose processor and an AI accelerator are often integrated on the same SoC or extended into closely coupled chiplet-based designs. Data moves through multiple stages of processing before results are returned to the application. While high-bandwidth data streams do not always require cache coherency, the information used to coordinate system operation does. Hardware-managed cache coherency shifts that responsibility from software to the coherent interconnect, enabling scalable coherency across heterogeneous systems.

The same architectural principles extend to multi-die systems. As designers partition larger devices across multiple dies, compute resources still need to exchange shared information efficiently. Arteris extends cache coherency beyond a single die, enabling coherent heterogeneous SoCs and chiplet-based designs to scale without pushing shared-data coordination back into software.

Coherent where it counts

The objective in edge AI systems is not to make every data transfer coherent, but to maintain coherency for the shared information that coordinates system operation. Most AI SoCs use both coherent and non-coherent interconnects, and the system does not use one approach everywhere. Cache coherency is used when multiple processing elements share data, whereas non-coherent interconnects move traffic that isn’t shared.

Efficient AI design depends on matching the interconnect architecture to the communication requirements of each part of the system. Rather than applying coherency throughout the SoC, designers use it only where shared state must be maintained across processing elements, while keeping the rest of the interconnect optimized for bandwidth, latency, and power efficiency.

Fig. 1: Example of an AI SoC architecture using coherent and non-coherent interconnects. Source: Arteris, Inc.

Arteris addresses non-coherent communication with FlexNoC interconnect IP, a physically aware network-on-chip (NoC) for complex SoCs. FlexGen smart NoC IP automates high-performance NoC design for advanced SoCs and chiplets. Ncore cache-coherent interconnect IP provides the coherent NoC fabric needed to keep a unified view of shared data.

The bigger story is a shift in chip design priorities. Hardware teams are no longer optimizing silicon in isolation. Engineers are designing hardware to reduce the software required to coordinate increasingly complex systems. Transistors spent making software simpler are not wasted. They are now part of the architecture.

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