Linear Optics And The Push To Scale AI Interconnects

AI clusters keep getting larger and more demanding. Training a trillion-parameter model means thousands of accelerators working in lockstep, and at that scale the interconnect stops being a supporting detail — every nanosecond of latency and every milliwatt of power shows up as a system-level cost.

Conventional optical interconnects weren’t built with that in mind. They rely on retimers and digital signal processors (DSPs) inside the optical module to condition the signal, and each of those parts adds power, latency, heat, and cost to every link in the system. That was tolerable at lower data rates. As deployments move toward 800G and 1.6T, it isn’t. Interconnects already draw roughly 27% of total data center power, a number that has grown 46x since 2010. At some point, the math forces a change.

Fig. 1: Scale-up and scale-out topologies using electro-optical links.

How linear optics simplify the module

Linear optics take a different route. Instead of putting DSPs and retimers inside the optical module, the linear approach moves signal processing back onto the host SerDes. What remains in the module is the essentials — linear drivers, modulators, photodiodes, and transimpedance amplifiers (TIAs) — and a much cleaner signal path with no DSP or retimer in the way.

The benefits are meaningful:

• Up to 50% lower power than conventional retimed optical modules
• Lower latency, since fewer processing stages mean data moves faster between accelerators
• Less heat, which matters a great deal in dense AI racks
• Simpler systems, with fewer components and fewer points of failure

Fig. 2: Retimed interface vs. linear interface comparison.

There is a trade-off. Once the DSP comes out of the module, the host PHY has to carry that load. It has to deliver clean signal integrity, strong equalization, and reliable data recovery across real channel conditions — and it has to do all of that while meeting the industry standards that make multi-vendor interoperability possible.

Proving it works at 112Gbps

Before linear optics can scale across the industry, designers need confidence that the technology clears rigorous, standardized performance requirements. That’s what the OIF-CEI-112G-LINEAR-PAM4 specification from the Optical Internetworking Forum (OIF) was written to provide: a common set of electrical limits, test points, and compliance methods for 112 Gb/s per-lane linear interfaces at 53 Gbaud PAM4.

The standard matters because it turns a fragile, vendor-specific implementation into a repeatable and interoperable one. Without it, every host-and-module combination would need custom tuning and pairwise validation — impractical at hyperscale. The real question was whether a host PHY could actually meet these requirements with margin to spare.

CEI-112G-LINEAR-PAM4 compliant PHY IP

Synopsys has developed the industry’s first 112G PHY IP that is fully compliant with the OIF-CEI-112G-LINEAR-PAM4 specification, and the measured results go beyond a basic pass.

On the transmit side, characterization shows strong signal integrity under standardized test conditions. Key metrics — voltage modulation amplitude (VMA), jitter, and eye closure — meet and in several cases exceed the CEI-defined limits across multiple temperatures.

On the receive side, jitter tolerance (JTOL) testing confirms the receiver can recover data reliably in the presence of injected sinusoidal jitter and real-world channel impairments. That resilience to timing variation and noise translates into fewer bit errors, fewer retransmissions, and stable link operation under stress — which is exactly what AI/ML networks need, since link stability is a persistent concern in these systems.

Together, the results confirm that the Synopsys 112G PHY meets, and in places exceeds, the OIF-CEI-112G-LINEAR-PAM4 specification, validating DSP-less host-to-module connectivity while maintaining signal integrity across the full link.

Fig. 3: Transmitter and receiver characterization / compliance results.

What it means for AI infrastructure

This is more than a compliance milestone. It shows that linear host-to-module connectivity is a viable, production-ready approach for next-generation AI and hyperscale systems. By moving complexity out of DSP-heavy optical modules and into the host, designers can reduce system power, latency, and thermal load without sacrificing signal integrity. And because the approach is standards-based, it delivers the multi-vendor interoperability that disaggregated AI infrastructure depends on.

The 112G PHY IP is part of a broader Synopsys ecosystem that includes MAC and PCS controllers, MACsec security, and verification IP, alongside the full Synopsys HPC IP portfolio spanning PCIe 6.x/7.0, CXL, UALink, die-to-die, memory interfaces, and foundation IP. Together they form a complete interconnect solution for scaling AI from chip to system.

Where this is heading

112G linear compliance is a milestone rather than a destination. The OIF has already started work on CEI-224G-Linear, extending DSP-less host-to-module signaling to 224 Gbps per lane. CEI-224G-LR/MR drafts are in member review, and two CEI-448G framework projects are now scoping the electrical interfaces for 3.2T and 6.4T links. The direction is clear: every future data rate will have a linear variant, and the PHY IP that meets those specs will sit at the center of each optical link.

That’s relevant because co-packaged optics (CPO) — optical engines integrated directly alongside switch ASICs, removing the copper trace altogether — is entering production. CPO depends on the same principle that 112G linear compliance validates: a host PHY that drives optics cleanly, with no DSP in the path. As CPO moves from scale-out into scale-up fabrics, standards-compliant linear PHY IP becomes the link between compute silicon and photonics.

Linear optics, CPO, chiplets, and standards-driven interoperability aren’t separate trends. They’re converging into a single architecture. With the industry’s first OIF-CEI-112G-LINEAR-PAM4 compliant PHY and an HPC IP portfolio spanning SerDes, PCIe, CXL, UCIe, and die-to-die interconnects, Synopsys is building toward it now.

For the full test methodology, transmitter and receiver characterization data, and detailed compliance analysis, download the whitepaper: Standards-Compliant 112G PHY for Linear Optics: Driving Efficient AI Infrastructure.

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