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New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation | Georgia Tech |
| ROBBIN: Rowhammer-Based Backdoor Injection during Inference | Northeastern University |
| An Open-Source Benchmark Suite of 3D-IC Testcases | UCLA |
| Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging | University of Michigan-Dearborn |
| Homo-metal-element Mediated Surface Modification of Sapphire for Robust Epitaxy of Wafer-Scale Single-Crystalline 2D Semiconductors | Peking University, ShanghaiTech University, Chinese Academy of Sciences et al. |
| Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors | Stanford University, SLAC |
| PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization | University of Alberta |
Find more semiconductor research papers here.
The post Chip Industry Technical Paper Roundup: Sep. 1 appeared first on Semiconductor Engineering.
Domain Tag
chip
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Semiconductor Engineering